ASIC Design Verification Engineer
$108k/y-$172.8k/y
Broadcoma day ago
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OnsiteFull-timeSenior
Summary
Broadcom is seeking an ASIC Design Verification Engineer to join their team in Irvine, CA. The role involves developing silicon products for Ethernet systems in the Cloud, focusing on high throughput Ethernet solutions that enhance AI/ML workflows.
About the Role
As an ASIC Design Verification Engineer, you will be responsible for verifying new designs using constrained random design verification methodologies with System Verilog and UVM. You will collaborate with worldwide design and architecture teams to develop leading-edge products, ensuring all aspects of design verification are covered while providing opportunities for technical leadership.
About You
Required:
- Bachelor's degree in a relevant field with 8+ years of related experience, or a Master's degree with 6+ years of experience, or a PhD with 3+ years of experience.
- Strong understanding of constrained random verification methodologies and experience driving completion via coverage closure.
Preferred:
- Experience with System Verilog (TB structures - Class, SVA, etc.) and UVM.
- Familiarity with scripting languages such as Python or Perl.
Benefits
- Competitive annual base salary range of $108k–$172.8k.
- Discretionary annual bonus and equity participation.
- Comprehensive benefits package including medical, dental, and vision plans.
- 401(K) participation with company matching.
- Employee Stock Purchase Program (ESPP) and Employee Assistance Program (EAP).
- Paid holidays, sick leave, and vacation time.
Broadcom
A global infrastructure technology leader built on more than 60 years of innovation, collaboration and engineering excellence.
Irvine, CA