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Summary
About the Role
About You
- Bachelor's degree in Computer Science, Computer Engineering, or a relevant technical field.
- 8+ years of hands-on experience in SystemVerilog/UVM methodology and/or C/C++ based verification.
- 8+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM methodologies.
- Experience in EDA tools and scripting (Python, TCL, Perl, Shell) for building verification environments.
- Experience in development of UVM based verification environments from scratch.
- Experience verifying GPU/CPU designs.
- Experience with high-speed interfaces like PCIe, DDR, Ethernet.
- Experience with Design verification of Data-center applications like Video, AI/ML, and Networking designs.
Benefits
- Competitive salary ranging from $173k to $249k per year.
- Bonus and equity options.
- Comprehensive benefits package.
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