About the Role

As an ASIC Engineer, Formal Verification, you will provide technical leadership in formal verification, propose and implement methodologies, work with architecture and design teams, define verification scope, create formal environments, and mentor engineers. You will also evaluate EDA solutions and build reusable environments for formal verification.

About You

Required:

Bachelor's degree in Computer Science, Computer Engineering, or a relevant technical field.
8+ years of experience in Design Verification.
5+ years of experience in Formal Verification.
Experience with Formal Verification applications including Datapath, sequential equivalence, Xprop, Clock Gating, and connectivity.
Proven understanding of Formal Verification methodologies and complexity reduction techniques.
Fluency in hardware description languages such as SystemVerilog and SVA.
Proficiency in scripting languages such as Python, Perl, or Tcl.
Experience with JasperGold or VC-Formal.

Preferred:

Experience in formal property verification of complex compute blocks such as DSP, CPU, GPU, or HW accelerators.
Experience with complex SoCs.
Experience with development of fully automated flows from specification to fully verified designs.
Experience with simulators and waveform debugging tools.

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ASIC Engineer, Formal Verification

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About the Role

About You

Benefits