Principal Physical Design Engineer (STA)
$209k/y-$250k/y
2 days ago
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OnsiteFull-timeSenior
Summary
Astera Labs is seeking a Principal Physical Design Engineer (STA) to join their team in San Jose, CA. The role involves driving the planning, coordination, and execution of the design of connectivity ASICs for leading cloud service providers.
About the Role
As a Principal Physical Design Engineer (STA), you will be responsible for end-to-end STA ownership across design stages, ensuring robust full-chip timing convergence. Your key responsibilities include driving timing closure from RTL through sign-off, developing and validating SDC constraints, managing I/O timing budgets, applying advanced sign-off methodologies, and providing actionable timing feedback. You will collaborate closely with RTL, physical design, and verification teams to achieve timing convergence.
About You
Required:
- Bachelor’s in Electrical Engineering or Computer Science required; Master’s preferred.
- 10+ years of experience in timing analysis and sign-off for complex SoCs in Server, Storage, or Networking applications.
- Expertise in timing constraints, STA methodology, and timing closure at both block and full-chip level.
- Strong knowledge of synthesis, place-and-route, extraction, and equivalence checking flows in advanced nodes (7nm or below).
- Proficiency with Cadence and/or Synopsys physical design/STA toolchains.
- Strong scripting ability (Tcl, Python, Perl).
- Ability to work independently with strong prioritization and a professional, customer-focused mindset.
Preferred:
- Familiarity with high-speed SERDES and Ethernet PHY timing challenges.
- Knowledge of ECO methodologies, DFT tools, and test coverage analysis.
- Experience working with IP vendors for both RTL and hard-macro integration.
- SystemVerilog/Verilog familiarity.
Benefits
- Competitive base salary range of $209k–$250k.
- Opportunities for professional growth and development.
- Inclusive work environment that encourages diverse ideas and backgrounds.
Astera Labs
Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe®, CXL®, and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable. Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable. Discover how we are transforming modern data-driven applications at www.asteralabs.com.
San Jose, CA