Sr. Staff Engineer, ASIC Design
$180k/y-$223k/y
Ayar Labs2 days ago
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OnsiteFull-timeSenior
Summary
Ayar Labs is seeking a Sr. Staff Engineer, ASIC Design to join their team in San Jose, CA. The role involves the design, bring-up, and debug of complex digital subsystems within an electro-optical digital SoC.
About the Role
As a Sr. Staff Engineer, ASIC Design, you will be responsible for developing detailed digital algorithm specifications, optimizing RTL in Verilog for complex electro-optical ASICs, and creating documentation for backend ASIC engineers. You will also bring up, evaluate, and debug in-house custom silicon, contribute to automated design methodologies, and work hands-on with high-speed interconnects and optical systems in a dynamic startup environment.
About You
Required:
- BS or MS in Electrical Engineering, Computer Engineering, or related fields.
- 5+ years of work or academic experience in ASIC design.
- Mastery of Verilog and SystemVerilog for both RTL design and verification.
- Proficient in ASIC verification tools (XCelium, VCS, Questa).
- Proficient in low-level programming languages (C, C++).
- Proficient in Python.
- Working knowledge of digital timing constraints and ASIC tool flows.
- Experience working on digital designs with multiple clock domains and clock dividers.
- Experience with SOC interconnect fabrics (AMBA AXI/AHB/APB).
Preferred:
- Proficient in ASIC synthesis tools (Genus, Design Compiler).
- Proficient in writing timing constraints and deep understanding of timing analysis.
- Working knowledge integrating custom blocks in a digital-top flow (LEF, lib, etc.).
- Performed silicon bring-up, debug, and evaluation.
- Working knowledge of FPGAs and/or microcontroller platforms.
- Working knowledge of the Cadence Virtuoso design environment, schematic entry, layout, and simulation.
- Experience with DFT methodologies and flows such as scan insertion, BIST, ATPG, etc.
- Knowledge of high-speed SerDes or SerDes components.
- Some knowledge of optics and control systems.
Benefits
- Competitive salary range of $180k–$223k.
- Opportunity to work in a dynamic startup environment with industry leaders.
Ayar Labs
Ayar Labs is transforming AI infrastructure by accelerating data movement. Recognizing that the complexity and size of AI models are increasing at a rate that traditional interconnect technology cannot handle, the company has developed the industry’s first optical I/O solution that enables customers to maximize the compute efficiency and performance of growing AI infrastructure, while reducing costs, latency and power consumption. Based on open standards and optimized for both AI training and inference, Ayar Labs’ optical I/O solution is backed by a robust ecosystem that enables it to integrate smoothly into AI systems at scale.
San Jose, CA