STA Engineer
a day ago
Highlight
OnsiteFull-timeMid
Summary
Sintegra Inc. is seeking a STA Engineer to join their team in San Jose, CA. The role involves closing subsystems and larger designs in semiconductor manufacturing.
About the Role
As a STA Engineer, you will be responsible for generating ASIC timing constraints and achieving timing closure. Your tasks will include utilizing industry-standard timing EDA tools, addressing timing convergence issues, and ensuring the functionality of various test modes.
About You
Required:
- Hands-on experience in ASIC timing constraints generation and timing closure.
- Expertise and advanced knowledge of industry standard timing EDA tools (Tempus preferred).
- Deep understanding and experience in timing closure of various functional and test modes.
- Expertise in timing convergence issues associated with deep-sub micron processes (crosstalk delay, noise glitch, POCV, IR-STA).
- Proficient in scripting languages (csh/bash, TCL and Python).
Sintegra Inc.
A leading provider of solutions for silicon integration Sintegra is a professional services company delivering value-added ASIC implementation solutions to our clients by deploying broad experience and extensive expertise, resulting in first-pass silicon success. Sintegra adds value by remaining on the leading edge of EDA and Design Methodologies to reign in challenges brought by ever increasing design complexities and shrinking geometries.
San Jose, CA