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Summary
About the Role
About You
- +5 years of experience as ASIC/FPGA designer
- Strong Verilog/System-Verilog experience
- Familiarity with simulation tools/environments and verification methodologies
- Strong team player with solid interpersonal skills
- BS/MS in Electrical Engineering or Computer Engineering from leading universities
- Experience with advanced design practices (Clock/Voltage domain crossing, Low Power Design, DFT)
- Design experience with DSP-oriented blocks
- Knowledge of Ethernet (100G and above)
- Scripting experience using Python, Perl, or TCL
AI is transforming industries at an unprecedented scale - but today’s data center infrastructure wasn’t built to keep up. As AI workloads grow more complex and data volumes double every two years, connectivity - not compute - has become the bottleneck. Retym is solving this challenge by delivering next-generation Coherent DSP solutions that provide high-performance, low-latency connectivity for AI infrastructure and data center interconnects. We are a semiconductor company driven by innovation, bringing together a world-class team of chip designers, optical networking experts, and leading investors to rethink how data moves in the AI era. Our purpose-built DSP technology delivers: Scalable, high-bandwidth interconnects for AI-driven data centers Power-efficient, high-performance networking that removes bottlenecks A coherent DSP provider that gives module makers more control and builds toward a more open, vibrant ecosystem With hyperscalers deploying AI across multiple locations and AI infrastructure requirements rapidly evolving, Retym is building the connectivity backbone for the future of AI. The future of AI isn’t just about compute - it’s about how we move data. Together, we are building a novel semiconductor technology that will transform the datacenter and telecommunications industries.